High output power quasi-square wave inverter circuit

ABSTRACT

A high output power inverter using a toroidal transformer, the inverter operating from a battery source, having, the toroidal transformer having a center-taped primary winding, the primary having a first end and a second end. A switching means for switching the first end and the second end of the transformer alternately to ground during alternate half cycles. A non-conductive interval being interposed between a first switch on-time and a second switch on-time. A control circuit for sensing the output voltage and for modulating the on-time of the switching means to maintain the output voltage within a predetermined range. An acoustic reference for a clock circuit, the clock circuit controlling the start of each power cycle. A current sense circuit for signaling overload when the on-voltage across the switching means exceeds a predetermined threshold. A shorting circuit for shorting the primary windings when the switching means is off.

[0001] This application is a Continuation-In-Part Application and formalization of Provisional Application Ser. No. 60/397,880 filed Jul. 22, 2002 and having a common inventor, Kamran Kazem and also U.S. Application 10/624,376 filed Jul. 21, 2003 claiming priority from

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to the field of power supplies and more particularly to the field of structures for holding and supporting power supply components that are required to withstand shock in the range of 100 Gs.

[0004] 2. Description of Related Art

SUMMARY OF THE INVENTION

[0005] The invention shows that

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1-27 are inclosed. Appendix pages 1-11 are photocopies of pages from Kamaran's notebook.

DETAILED DESCRIPTION

[0007] The invention is a HIGH OUTPUT POWER QUASI-SQUARE WAVE INVERTER CIRCUIT used in connection with a 28Vdc to 115 Vac 2.5 KW RUGGEDIZED INVERTER STUCTURE. The HIGH OUTPUT POWER QUASI-SQUARE WAVE INVERTER CIRCUIT and rugidized structure comprises a base, the base having a forward and rear rectangular tube separated by an integral base plate, the tubes and integral base plate being formed from rectangular aluminum having a thickness greater than 0.125 inches

[0008] A vertical U-Shaped frame formed from plate aluminum having a thickness of 0.187 inches spaced apart in parallel relation at a distance of approximately 18 inches. The U-Shaped frame having a left, right and rear wall, each wall having a respective inner and outer surface. The U-Shaped frame is integral in that the left and right walls are coupled to opposing edges of the rear wall and it is homogenous in that it is formed from a single plate of aluminum having no joints, seams or welds.

[0009] The tubes and integral base plate operating to stiffen the base plate, the front and rear rectangular tubes extending across the rear of the base to couple the left side of the vertical U-Shaped frame to its right side.

[0010] A flat aluminum plate coupled to the top of the base. The flat aluminum plate is approximately 0.250 inches thick. The flat plate extends approximately {fraction (2/3)} the distance between the left and right sides of the vertical U-Shaped frame which are separated by approximately 18 inches.

[0011] A toroidal transformer, having a diameter of about 9.5 inches is mounted to the flat aluminum plate. From mathworld.com. the word toroid characterizes a surface of revolution obtained by rotating a closed plane curve about an axis parallel to the plane which does not intersect the curve. The simplest toroid is the torus. The word is also used to refer to a toroidal polyhedron

[0012] The toroid core appears to be near fully wound except for a central hole region reserved for a mounting bolt. The toroid has a base surface, a top surface and the central hole. The space between the transformer base surface and the flat aluminum plate is filled with a thermally conductive resin. The resin is an epoxy filled with aluminum powder to enhance its thermal conductivity. The central hole of the toroid is filled with loaded epoxy except for the hole. The wire that is used is for the secondary is square in cross section and is believed to be number 10 wire. The temperature specified for the wire insulation is 200 degrees centigrade. That is class H for the transformer. Winding resistance, turns ratio, operating voltage and things like that are specified in a source control document that is used to purchase the transformer. The transformer is the main power transformer is secured to the plate by a hold down bolt that passes through a pre-cast hole in the loaded epoxy fill, the hole passing from the top surface of the toroid to the bottom surface.

[0013] A G-10 fiberglass-epoxy board plate, formed from fiberglass, the circuit board plate being positioned on the top surface of the toroid. Three left and right primary terminals on the plate are coupled to the left and right ends of the transformer's primary winding and an input center tap terminal is coupled to a primary winding center tap. Two output terminals are coupled to the left and right ends of the secondary winding. No center tap is used on the secondary. The secondary voltage is 120VAC nominally quasi-square wave or quasi-sine wave in shape and 60 Hz in frequency. The dead time is established by the third harmonic and is about three milliseconds. During the dead time, the OFF-TIME Shorting circuitry shorts the two ends of the primary winding together to form a temporary common node but does not short to common node to ground.

[0014] Heat is removed from the core and the copper wire in the window of the transformer via the thermally conductive potting material and then through the plate from which the heat is coupled to the base of the integral base plate in the base.

[0015] A left and right power module are coupled to respective left and right inner wall surfaces of the vertical U-shaped frame.

[0016] Each power module has a large aluminum base plate with a thickness of approximately 0.250 inches.

[0017] A power FET circuit board having an inner surface and an outer surface is coupled to each respective base plate. Each power FET circuit board has two rows of ten each IRF540; 100 V, 28A power MOSFETs coupled in two parallel sets. The first set is comprised of 16 of the 20 MOSFETs and the second set is comprised of the remaining 4 out of 20 MOSFETs. The set of 16 MOSFETs are used for the power switching, while the set of 4 MOSFETs are used for the Transformer OFF-TIME SHORTING.

[0018] Each FET has a metal mounting tab. Each FET has a plastic body coupled to the metal mounting tab Each FET has a Gate, a drain and a Source lead extending from its respective plastic body. The drain lead of each FET is electrically common with its respective metal mounting tab.

[0019] The metal mounting tabs of each FET is pressed against a strip of insulating material that is coupled to the base plate. The insulating material is called ISOSTRATE, and is made by Power Devices Corporation, located in Laguna Hills, Calif. It is a type of pre-greased Kapton. The strip of insulating material prevents electrical contact between the drain and the large aluminum base plate. The three leads of each FET are formed for insertion into printed circuitry on the outer surface of the respective circuit board.

[0020] A strip of high durometer neoprene rubber material made by 3M Company, part number: SJ6008, is inserted between a plane formed by the plastic bodies of the FETs and the respective power FET circuit board outer surface. A high durometer rating implies that the material compresses only slightly under load.

[0021] Mounting screws being inserted through the power FET circuit board inner surface to its outer surface and then to the respective large aluminum base plate to force the power FET circuit board toward the respective large aluminum base plate, the neoprene strip being compressed between the power FET circuit board outer surface and the plastic bodies of the FETs, the plastic bodies transferring the load imposed by the neoprene strip to the metal tabs pre-loading the tabs against the insulation strip on the large aluminum base plate. Three screws are used to force the circuit board against the rubber strip and thence against the plastic bodies of the row of ten FETs thereby obtaining fairly even pressure.

[0022] A control module is coupled to the inner surface of one of the power FET circuit boards. Two bolts are used on the lower edge and three are used along the top edge. Two Z-shaped brackets are used.

[0023] Power cables pass through the rear wall of the vertical U-Shaped frame.

[0024] RUGGEDIZIDED 28Vdc to 115 Vac 2.5 KW INVERTER CIRCUIT was described by INVENTOR KAMRAN KAZEM in connection with the schematic he provided as follows.

[0025] The outputs are at 8C on the schematic to the power boards. The controller is an SG1526. Although it has an internal oscillator, we have used a crystal controlled oscillator for greater precision. I start with IC U4, a 4060 CMOS chip in conjunction with Crystal Y1 which is actually a tuning fork resonator. It is not an actual crystal. It oscillates at an audio frequency of 15.36 KHz.

[0026] The 15.36 KHz signal is divided down to 120 Hz at the sync input, pin 12 of U2, the SG1526 controller. U3B is a FF, an MC4013 that provides a divide by 2 function. On the input side of the U3B FF, the frequency is 240 Hz. At U4, the previous stage, the frequency is 480 Hz.

[0027] Current sensing is achieved using the on-resistance of the power FETs on the power boards. The signal is sensed and rectified by bridge BR1. The output of BR1 is passed to comparator U15C which compares the resulting rectified signal with a dc level that is adjusted using R63 to set the threshold level. The threshold is set to not exceed 2.5 volts.

[0028] The circuit is a synchronous circuit. The sense voltage is gated on when the FETs are conducting. U11 gets a signal from the main oscillator or U4 to gate the signal on as the FETs are driven into conduction. U15D is a one shot circuit. The MC1403 is a D-Flip Flop. The output of that U11B FF is the Overload Signal. The Q output of Q11B normally remains high. It goes low to indicate an overload. The flip flop is tied to the U4 master clock. Data gets clocked in every half cycle.

[0029] U15D is a timing circuit. It controls the time that the converter is allowed to continue to run for a few seconds after the detection of an over-current or fault condition. This delay accomodates the typical surge requirement of a motor starting into an initial locked rotor or the high input current to the filament of a lamp load. A motor can come up to speed and run within a few seconds with not timer trip. If the over load continues past the time threshold, U15D timing circuit. It controls the D-input that is the data input to the U11B flip-flop. If the data is high, then it clocks through a high. That is its normal state. If a fault condition persists, it times out and goes low. That shuts the Inverter output down completely.

[0030] Moving to B6 on the schematic, and U15A and U15B. These Ics are used to sense input over voltage and under voltage. If the battery driving the 28V buss is too low, i.e. below 18 VDC, we terminate inverter operation so as not to kill the battery. If the battery voltage is above 33 VDC inverter operation is terminated to prevent output voltage over stress to the loads coupled to the outputs of the inverter. A high input voltage with cause the inverter operation to shut down instantly. A low voltage detect signal will not terminate Inverter operation immediately to accommodate line drops due to high current start loads. The U15D timer controls the delay, which is set to about 7 seconds. Indicator lights are provided.

[0031] The reset circuit includes the U11B F/F that controls weather the unit is allowed to run or the output will be inhibited. A reset switch is shown between M17 at location A7 and signal M23 at location A5 that is also part of the timer. If after the Inverter is reset, you have a low battery, you discover that you have a low battery, capacitor C₂₀ is part of the U15B timer, discharges terminating Inverter operation by driving the inverting input of U15D lower than the 6V reference.

[0032] In the case of a high input voltage situation, note that there is an additional diode D22 that goes right to capacitor C20 and will discharge it triggering the F/F U11 to go to the low state. That terminates operation instantly. The low battery detection circuitry does not have a similar diode. The timing circuitry allows C20 to discharge through R47 and provides six to 7 seconds to allow the battery to come back up if the drop was due to a momentary surge.

[0033] The circuitry in the center of the drawing is the ac regulation circuitry. U16 is a quad LM324 Op Amp. Three stages are used in the AC Regulation Feedback Loop. In this push-pull design, as you might recall, the drains of the FETs or the collectors of bi-polar switches go to double the input voltage. We typically see twice the 28 Vdc level or 56 Volts peak there. The minimum voltage fed into the U16 circuit is the battery voltage of 28 VDC nominal. U16A is a level shifting circuit translating the 56 V peak level down to about 10V, and also translating the minimum level of 28V down to the control circuit reference level or circuit ground. Pin 1 of U16A is a divided down signal that goes from about 0 to 10 V that goes up and down with the output pulses. The result is an analog output voltage pulses that is referenced to control ground. That is fed to the inverting input of U16B, which adds a little DC into the signal that helps the load regulation. U16C, the error-amp stage, is the main regulator that controls level of the AC output voltage to keep it at 120 VAC. On the non-inverting input of U16C pot R8 is the output voltage adjustment pot. The pot is supplied from a precision 12 V reference. The inverting input receives a signal from the output of U16A followed by U16B. The output of that, the 4016 analog switch is in series with the error amp output, U16C, so we can open that signal if we want to. That is then fed up to U2 the 1526 to control the pulse width. The control signal is a dc level in the range of 0-4 VDC Off time shorting is partly generated by the sync signal from U2 because that signal is active both outputs of the 1526 are off. During that interval, both power board outputs are off. We take that signal to U17C to buffer it, then to U17A to invert it and it is then amplified by transistor Q3. The two PWM output signals are wired or'd together with diodes D26 and D42. The or'd signal is high when the outputs are high and low only when both outputs are low. That is the condition when we want the off-time shorting to be enabled.

[0034] Q3, is a 2N2907A small-signal transistor. The output of that goes through a series diode, D39 and feeds the gates of the off-time shorting transistors on both the left and right power boards, which shorts the two halves of the primary windings together, but not to ground to allow the primary current to re-circulate and degenerate to reset the core. This also helps keep the output waveform clean during the power transistor off-time.

[0035] A VIBRATION AND SHOCK TEST WAS MADE ABOUT MID AUG. 7^(th) and 8^(th) 2001 which tests were witnessed by a government QAR representative from the Irvine, Calif. DCMO office.

[0036] None of the design existed in the proposal stage. You sent the proposal in before you came up with the schematic. Yes that is the case. There was development going on right up to the testing.

[0037] The use of the SG1526 helps reliability and reparability of the unit. The use of the military type crystal and the use of the high-current power FET driver IC, U9 at 5C on the drawing, allows us to cascade far more than the three inverters that the competition can put in parallel. We can cascade up to ten units, which contain about 400 power MOSFETs.

[0038] The toroid transformer uses a tape-wound silicon steel core.

[0039] Tape prepared on Jul. 21, 2002

[0040] Kamran Kazam,s comments on pages from his lab book, the pages starting from a date of Jul. 24, 2001. The page numbers in the log book did not come out in the copies. Page 67 starts the information entered on Jul. 24, 2001. The copies of the log book pages are numbered 1-10 at the bottom of each page.

[0041] In the middle of the page, the entry titled minimum changes required on the MDL (Magnetic Design Laboratories) control board for TACOM test of 2.5 KW Inverter using 2.5 K bleeder. Referring to FIG. 1, add 2 each 1N4148 diodes. The diodes are circled on FIG. 1. The cathodes are common and are connected to M5, a test point. The diodes are designated D52 and D53. One anode goes to U14-11 and the other goes to U14-9. The second item on the page of the note book is add one each 1N4148, cathode to U15-9 and the anode to U15-12. That diode is designated D47 on the schematic. It is not clear from the schematic subsection I am printing that will be titled page or FIG. 2. The U15-12 node provides a battery return signal or reference level with is the ground for the schematic. The purpose of D47 diode is to prevent negative spikes generated by the transformer from disrupting the current limiting function that is provided by U15-C located on FIG. 2 at A-7.5.

[0042] In the log book at the next subsection, we find “Replace D29 with a jumper. That change is also shown on FIG. 2 between the output of comparator U15 and the reset input to the load latch U11-B. The diode D29 diode is made necessary for the cascading of units that will occur in the Tank applications. D29 eliminates the isolation between the current comparator U15-C which is between the master and the slave. Very little of the control board circuitry in the slave has bias power to work. That is the one area where the slave controls board circuit is powered up and functions. That is what we call the main current limit protection. That is what we call the main current limit comparator. So any slave unit that is being overloaded will shut down the other units including the master inverter. The control circuit in the master unit is used to control the pulse width modulation of all of the slave units. Interruption is controlled via the M2 signal right under the D29 diode as shown. So the D29 is replaced with a jumper.

[0043] Subsection 5 on the notes in the Log book: The next subsection in the notes at page 1, item 4 is an instruction to delete R48 as show on FIG. 3. The component is located between 17 C and D-24 located at A-5 on the schematic. It was not being used so the part was deleted.

[0044] The next log book entry delets R37 which is over in the idel circuit. The part or circuit is not used. The idel circuit is deleted to allow the cascaded military Tank units to operate properly since the outputs of each are separate.

[0045] Item 6 deletes R59 on FIG. 2 and appears beneath diode D-29 discussed above. It is a one meg resistor and its function again is related to the number of units to be cascaded. If two units are cascaded, the value drops to 500K. At three units are connected, the value drops to 333K. The impedance gets too low and starts to discharge capacitor C-21 which is a critical timing cap for the current limit circuit. It discharges that cap too fast so rather than have that condition, we simply delete R59.

[0046] On log book page 68, page 2 in the copies, changes were listed as checked that were necessary for multiple unit operation. A note appears that informs that both have a 2.5 K ohm 10 W resistor on the control board on the bread board in an unused section. The function of the bleeder circuit is to insure that a sufficient minimum load is imposed to cause the idel circuit to think that the system is in the normal high output power state even when that is not the case. The idel circuit is set to trip at about 5 Watts. If the load is under the trip level, the cirucit goes into a battery saving mode so that the battery is not discharged. The system drops the output voltage from 120 to 45 to 60 Vac. The introduction of the bleeder resistors insures that the circuit will not enter the ide model. However this plan did not work and other changes had to be made to obtain satisfactory operation.

[0047] On page 72 and 73 dated Jul. 25, 2001 have to do with testing a Harts brand Inverter that came with a dual housing assembly from the Tank command. On page 74 in my lab book dated Jul. 25, 2001, at item one, at the top of page number 3. after the phrase “Fix startup out of ctl problem: Added 10K resistor from U48-1 to U48-2 to help the control loop remain in control before of the reset signal. You would start up a first unit some times and it would start up not particularly in control. The change was introduced to get the unit to start in a controlled and predictable manner. The addition of the 10K resistor from U8-1 to U8-2 was an attempt help the control loop stay in control before reset. This is an attempt to bi-pass the analog switch that is turned on and off by the idel circuit so that it will have at least a partial input from the error amplifier while it was in idel and as it comes out of idel during start up. You will see a circled area on FIG. 4 where the part was removed. There is a jumper there W10 that was inserted in place of the resistor at a later time. 

1. A high output power inverter circuit coupled to obtain power from a voltage source (Vb) such as a battery service, the voltage source having a ground return line (Vr), the high output power inverter circuit comprising: a toroidal transformer having a primary and a secondary winding, the primary winding having a first end, a second end and a center tap, the center tap being coupled to the voltage source, a first and second switch to conductively couple the first end and the second end of the transformer alternately to the ground return line (Vr) during alternate half cycles of successive power cycles for respective and successive first and second on-time intervals, the toroidal transformer secondary providing a quasi-square wave output voltage a pulse-width modulator and driver circuit for driving the first and second switch into conduction for each on-time during alternate half cycles of successive power cycles, and for interposing a dead-time or non-conductive interval between the first and second on-time intervals and during the interval preceding the start of any subsequent first on-time interval, a control circuit for sensing the on-time voltage on a non-conducting second end or non-conducting first end of the primary winding during the on-time of the respective conducting first or conducting second switch and for modulating the on-time of the switching means to maintain the quasi-square wave output voltage within a predetermined range, and an output current-voltage sensing circuit means for measuring the load current by measuring the on-time voltage on the conducting first end or second end of the primary winding with respect to the ground return line (Vr) during the on-time of the respective first or second switch, and for terminating the switching means on-time in response to a predetermined on-time voltage threshold being exceeded.
 2. A high output power inverter from a dc voltage source having a service line providing 22 to 36 Vdc from a battery service, the source having a ground return line, the power inverter comprising: an input transformer having a primary and a secondary winding, the primary winding having a first end and a second end and a center tap, switching means for switching the first end and the second end of the transformer alternately to ground during alternate half cycles, a dead time or non-conductive interval being interposed between the first end and the second end of the transformer being switched to ground, a control circuit for sensing the output voltage and for modulating the on-time of the switching means to maintain an output voltage within a predetermined range, an acoustic reference for a clock circuit, the clock circuit controlling the start of each power cycle, and means for monitoring the output current by measuring the reflected load current in the primary winding, the transformer secondary having a first and second end, the first and second ends being connected to output terminals.
 3. The high output power inverter circuit of claim 1 wherein the output current-voltage sense circuit means further comprises: means for measuring the load current by measuring the on-time voltage on the conducting first end or the conducting second end of the primary winding with respect to the ground return line (Vr) during the on-time of the first or second primary switch.
 4. The high output power inverter circuit of claim 1 wherein the output current-voltage sense circuit means further comprises: means for measuring the load current by measuring the on-time voltage on the conducting first end or the conducting second end of the primary winding with respect to the ground return line (Vr) during the on-time of the first or second primary switch, and a latch circuit characterized to toggle to all over-current state in response to a predetermined sensed voltage being exceeded, the over-current output state of the latch circuit providing an over-current signal to terminate the switching means on-time thereby turning off the switching means.
 5. The high output power inverter circuit of claim 1 wherein the control circuit for alternately sensing the voltage on a non-conducting first end or second end of the primary winding during the on-time of the second or first switching means and for modulating the on-time of the switching means to maintain an output voltage within a predetermined range further comprises: a first and second amplifier coupled to receive, scale and filter the first and second non-conducting primary voltages to form a control voltage, the control voltage being coupled to an averaging filter to provide a filtered control voltage, the filtered control voltage being coupled to the switching means control voltage input, the switching means modulating the on-time to minimize the difference between the filtered control voltage and a reference voltage to thereby maintain the output voltage within a predetermined range.
 6. A high output power inverter circuit coupled to obtain power from a voltage source (Vb) such as a battery service, the voltage source having a ground return line (Vr), the high output power inverter comprising: a toroidal transformer having a primary and a secondary winding, the primary winding having a first end and a second end and a center tap, the center tap being coupled to the voltage source, a first and second switch to conductively couple the first end and the second end of the transformer alternately to the ground return line (Vr) during alternate half cycles of successive power cycles for respective and successive first and second on-time intervals, the toroidal transformer secondary providing a quasi-square wave output voltage, a pulse-width modulator and driver circuit for driving the first and second switch into conduction for each on-times during alternate half cycles of successive power cycles, and for interposing a dead-time or non-conductive interval between the first and second on-time intervals and during the interval preceding the start of any subsequent first on-time interval, a control circuit for sensing an on-time voltage on a non-conducting second end or non-conducting first end of the primary winding during each on-time of the respective conducting first or conducting second switch and for modulating the on-time of the first and second switch to maintain the quasi-square wave output voltage within a predetermined range, and a shunt switching circuit for connecting the first end of the primary winding to the second end to the primary winding during a dead-time between each respective on-time.
 7. The high output power inverter circuit of claim 6 wherein the shunt switching circuit further comprises: FET shunt switches responsive to a shunt drive signal to connect the first end of the primary winding to the second end of the primary winding during the dead-time of the first and second switching means.
 8. The high output power inverter circuit of claim 6 wherein the control circuit further comprises: a first and second amplifier coupled to receive, scale and filter the first and second non-conducting primary voltages to form a control voltage, the control voltage being coupled to an averaging filter to provide a filtered control voltage, the filtered control voltage being coupled to the switching means, the switching means modulating the on-time to minimize the difference between the filtered control voltage and a reference voltage to thereby maintain the output voltage within the predetermined range.
 9. The high output power inverter circuit of claim 6 wherein the shunt switching circuit further comprises: a dead-time detection and shunt drive circuit having a first comparator coupled to compare the amplitude of the first and second non-conducting primary voltages with a predetermined portion of the voltage source (Vb) and to output a dead-time signal in response to the non-conducting primary voltage exceeding the predetermined portion of the non-conducting primary voltage, the dead-time signal being, coupled to the shunt driver circuit to command the shunt switches into the conductive state.
 10. The high output power inverter circuit of claim 6 wherein the shunt switching circuit is further characterized to provide a shunt drive signal to first and second FET shunt switches connecting the first end of the primary winding to the second end of the primary winding during the dead-time of the first and second switching means.
 11. The high output power inverter circuit of claim 6 further comprising: an output current monitor circuit for measuring the output load current and for interrupting the drive signal to the shunt switching circuit when the measured output load current is below a predetermined limit to conserve operational power dissipation by interrupting shunt drive signal power during periods of very low output power.
 12. The high output power inverter circuit of claim 6 wherein the output load current low limit detection circuit further comprises: a center-taped winding on a core having a first and second end, the first end being coupled to be in series with ground return and the first switch means, and the second end being coupled to be in series with the ground return and the second switch means, a slot being cut in the core, a Hall Effect device being inserted in the slot, the Hall Effect device outputting a load-current signal, a hall-effect amplifier being coupled to be responsive to the load-current signal for outputting a buffered and scaled load-current signal, a comparator responsive to the load current signal for comparing the load-current signal with a predetermined reference and for outputting a shunt interrupt signal to the shunt circuit to interrupt the shunt drive signal
 13. The high output power inverter circuit of claim 6 further comprising: a low battery voltage, time delay and interrupt circuit for comparing the voltage source voltage (Vb} when measured with respect to the ground return line (Vr) to a predetermined low voltage source reference voltage and for outputting a low voltage source signal in response to the voltage source voltage falling below the predetermined low voltage source voltage limit, the low voltage signal being coupled to the over-current delay and latch circuit to set the over current latch after a predetermined time delay.
 14. The high output power inverter circuit of claim 6 further comprising: a high battery voltage interrupt circuit for comparing the voltage source voltage (Vb} when measured with respect to the ground return line (Vr) with a predetermined high voltage source reference voltage and for outputting a high voltage source interrupt signal in response to the voltage source voltage rising above the predetermined high voltage source voltage limit, the high voltage source signal being coupled to the over-current delay and latch circuit to set the over current latch with no predetermined time delay.
 15. A high output power inverter circuit coupled to obtain power from a voltage source (Vb) such as a battery service, the voltage source having a ground return line (Vr), the high output power inverter comprising: a toroidal transformer having a primary and a secondary winding, the primary winding having a first end and a second end and a center tap, the center tap being coupled to the voltage source, a first and second switch to conductively couple the first end and the second end of the transformer alternately to the ground return line (Vr) during alternate half cycles of successive power cycles for respective and successive first and second on-time intervals, the toroidal transformer secondary providing a quasi-square wave output voltage, a pulse-width modulator and driver circuit for driving the first and second switch into conduction for each on-times during alternate half cycles of successive power cycles, and for interposing a dead-time or non-conductive interval between the first and second on-time intervals and during the interval preceding the start of any subsequent first on-time interval, a control circuit for sensing an on-time voltage on a non-conducting second end or non-conducting first end of the primary winding during each on-time of the respective conducting first or conducting second switch and for modulating the on-time of the first and second switch to maintain the quasi-square wave output voltage within a predetermined range, an output current-voltage sensing circuit means for measuring the load current by measuring the on-time voltage on the conducting first end or second end of the primary winding with respect to the ground return line (Vr) during the on-time of the respective first or second switch, and for terminating the switching means on-time in response to a predetermined on-time voltage threshold being exceeded. and a shunt switching circuit for connecting the first end of the primary winding to the second end to the primary winding during a dead-time between each respective on-time.
 16. The high output power inverter circuit of claim 15 wherein the control circuit further comprises: a first and second amplifier coupled to receive, scale and filter the first and second non-conducting primary voltages to form a control voltage, the control voltage being coupled to an averaging filter to provide a filtered control voltage, the filtered control voltage being coupled to the switching means, the switching means modulating the on-time to minimize the difference between the filtered control voltage and a reference voltage to thereby maintain the output voltage within the predetermined range.
 17. The high output power inverter circuit of claim 15 wherein the shunt switching circuit further comprises: a dead-time detection and shunt drive circuit having a first comparator coupled to compare the amplitude of the first and second non-conducting primary voltages with a predetermined portion of the voltage source (Vb) and to output a dead-, time signal in response to the non-conducting primary voltage exceeding the predetermined portion of the nonconducting primary voltage, the dead-time signal being coupled to the shunt driver circuit to command the shunt switches into the conductive state.
 18. The high output power inverter circuit of claim 15 wherein the output load current low limit detection circuit further comprises: a center-taped winding on a core having a first and second end, the first end being, coupled to be in series with ground return and the first switch means and the second end being coupled to be in series with the ground return and the second switch meals, a slot being cut in the core, a Hall Effect device being inserted in the slot, the Hall Effect device outputting a load-current signal, a hall-effect amplifier being coupled to be responsive to the load-current signal for outputting a buffered and scaled load-current signal, a comparator responsive to the load current signal for comparing the load-current signal with a predetermined reference and for outputting a shunt interrupt signal to the shunt circuit to interrupt the Shunt drive signal.
 19. The high output power inverter circuit of claim 15 further comprising: a low battery voltage, time delay and interrupt circuit for comparing the voltage source voltage (Vb} when measured respect to the ground return line (Vr) with a predetermined low voltage source reference voltage and for outputting a low voltage source signal in response to the voltage source voltage falling below the predetermined low voltage source voltage limit, the low voltage signal being coupled to the overcurrent delay and latch circuit to set the over current latch after a predetermined time delay.
 20. The high output power inverter circuit of claim 15 further comprising: a high battery voltage interrupt circuit for comparing the voltage source voltage (Vb} when measured respect to the ground return line (Vr) with a predetermined high voltage source reference voltage and for outputting a high voltage source interrupt signal in response to the voltage source voltage rising above the predetermined high voltage source voltage limit, the high voltage source signal being coupled to the over-current delay and latch circuit to set the over current latch with no predetermined time delay. 